https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485

The 10300B STAT signals in least significant order are:
/WR - CPU pin 22
/IORQ - CPU pin 20
/RFSH - CPU pin 28
/M1 - CPU pin 27

/WR is fed three times through a 74LS240 inverting buffer/driver for a STAT
signal.
/IORQ is fed once through a 74LS240 inverting buffer/driver for clock signal,
and twice for a STAT signal.
/RFSH is fed once through a 74LS241 non-inverting buffer/driver for a clock
and STAT signal.
/M1 is fed once through a 74LS241 non-inverting buffer/driver for a STAT
signal.

Maybe the multiple passes for /WR and /IORQ are to delay those signals by a
few ns.

That is from the Model 64683A Interface Module Z80 Service Information manual
part number 64683-90903. I only have a photocopy of the manual. I'll see if I
can get it scanned when I have time.